The emergence of cloud-based internet services, artificial intelligence, and cryptocurrency has initiated a strong growth of processing power in data centers worldwide. In combination with rising electricity and real estate prices, this trend creates a clear need for highly efficient and compact server power supplies.

To achieve the required higher power density, the following three main contributors must be considered:

  1. Increased efficiency to maintain an acceptable total power loss in a given volume. This drives the transition to new topologies and technologies. A great example is the transition from the conventional silicon classic-boost PFC to the gallium nitride/silicon carbide totem-pole PFC.
  2. Improved packages and thermal solutions that can dissipate the power away from the device junction to heatsinks and ambient. This becomes more challenging in smaller surface-mount device (SMD) packages that are the main enabler for high-density converters.
  3. Optimized system design and switching frequency to achieve maximum density without violating efficiency requirements or temperature-rise limits. This leads to an increased switching frequency, driving the transition from conventional to new packages and thermal solutions.

Typically, state-of-the-art, high-efficiency power supplies are comprised of a bridgeless PFC stage, such as a totem-pole stage, and a resonant DC/DC stage, such as an LLC converter (see Figure 1). An example specification of a server supply is Vin = 180–277 V, Vout = 48 V, Pout = 3 kW.

Figure 1: Server supply comprising a totem-pole PFC and an LLC DC/DC converter

To quantify the achievable performance tradeoff between efficiency and power density, the Pareto optimization method is applied. This method systematically considers all available degrees of freedom in the design of the different converter systems. By employing detailed system and component models, it identifies the optimal designs positioned on the Pareto front. The efficiency is calculated for 50% of the rated output power and includes both PFC and LLC stage losses.

The Pareto front for the entire server supply system is calculated, and the optimization results are shown in Figure 2. The graph indicates that efficiencies close to 98.2% can be achieved for medium power densities (~40 W/in.3), while designs with more than 80 W/in.3 have efficiencies below 97.5%. Another important observation from this figure is the higher switching frequency of the LLC stage required for higher-density designs. These observations confirm the necessity of packages operating at a higher frequency with higher efficiency.

Figure 2: Optimization results of the entire server power supply showing efficiency versus density, with the optimal LLC stage frequency

SMD packages used in SMPS topologies

Infineon offers a larger portfolio of bottom-side cooling (BSC) and top-side cooling (TSC) packages that fulfill the higher-power and higher-density trends in server switch-mode power supply (SMPS) applications. This section discusses and compares the different packages concerning topics such as assembly, thermal performance, and electrical parasitics.

Assembly implementations of BSC and TSC packages

Bottom-side cooling

Figures 3 and 4 show the principal cooling concept for BSC and TSC. In both cases, the SMD package is mounted on the PCB, usually via a reflow-soldering process. For BSC, the main heat flux is directed from the device heatsink (exposed pad) on the bottom of the package through the PCB to an external heatsink mounted on the opposite side of the PCB. Therefore, thermal vias below the package and through the PCB are needed for heat transfer when using an FR4-based PCB. On the backside of the PCB, the external heatsink is mounted on the area with the thermal vias. The heatsink and the PCB are electrically separated via a thermal interface material (TIM). Quite often, a foil with a thickness in the range of 100–500 μm is used as TIM, which has, in the best case, a good thermal admittance (λ). This leads ideally to a low thermal impedance (Zthja) for the overall system.

Figure 3: Example solution using bottom-side cooling
Figure 4: Example solution using top-side cooling

The PCB has a certain thickness, influenced by the number of necessary Cu layers for circuit design and a density limitation for the thermal vias. Because of that, the effective cross-sectional area for heat transfer through the PCB is reduced compared with the area for heat transfer offered by the device heatsink. This is the first bottleneck. The second bottleneck is the TIM, having a much lower λ than the device heatsink and the external heatsink.

In some cases, replacing the FR4-based substrate with insulated metal substrate (IMS) allows for a higher heat flux without exceeding the maximum device or PCB temperature. Especially for single-layer PCB designs, neither thermal vias nor additional TIM are needed. The external heatsink can be saved because the aluminum core of the board is used as a heatsink. However, although Zthja is reduced, the number of temperature cycles on board (TCoB) is reduced, especially for non-leaded SMD packages like TO-leadless (TOLL) or ThinPAK caused by the rigid IMS-based PCB compared with the more flexible FR4-based PCB.

Top-side cooling

In TSC packages, the device heatsink on top of the package is interfaced directly to the external heatsink through the TIM (Figure 4). In this case, there is no heat passing through the PCB and thermal vias therefore eliminating their thermal impedance from the total thermal impedance. This leads to enhanced thermal conductivity and higher package maximum power dissipation.

Moreover, another advantage of TSC packages is the free area on the opposite PCB side that can be used to place other devices such as gate drivers and passive components, as well as space for signal routing directly below the package body.

For a good thermal interface, it is recommended to press the heatsink with a certain force on the TSC device. In the case of leaded SMD packages with a positive package standoff (Figure 5, left), this force and other temperature-cycling–induced forces are absorbed by the package leads, resulting in very good TCoB of 2,000 cycles in the case of QDPAK.6

In case of a negative package standoff (Figure 5, right), other considerations are needed for the PCB design to avoid system reliability issues, which could cause additional effort and complexity for the system design and manufacturing. A negative package standoff has the advantage of reduced Zthja because of its reduced package height tolerance, leading to a thinner TIM thickness. However, when considering other tolerances like PCB warpage, especially with larger PCB size and multiple power devices using a common heatsink, the thermal advantage of a negative package standoff becomes less important.

Figure 5: Standard positive package standoff (left) and negative package standoff (right). The copper pad below the package body is beneficial as mechanical support of well-defined height and high board-level reliability in case of a negative standoff.2

For the common heatsink approach, Figure 6 shows schematically the TIM stack between device and heatsink, which consists of insulation foil and gap filler in this example. The gap filler is used for compensating device-, heatsink-, and PCB-related manufacturing tolerances. Using only a gap filler for heat transfer, a reliable insulation between the device and external heatsink must be ensured. Additionally, the gap filler material must fulfill the necessary breakdown rating, and enclosed particles within the gap filler or blowholes during PCB assembly need to be prevented. In general, a clean manufacturing ambient for PCB assembly can lower the risk of system failures caused by pollution during system manufacturing.

Electrical isolation foil and gap filler between the external heatsink and the device.
Figure 6: Electrical isolation foil and gap filler between the external heatsink and the device

For further improved Zthja and dynamic power dissipation for TSC, the implementation of an intermediate heat spreader is a good option, as shown in Figure 7. The thermal capacity of this additional heatsink can store for a certain time (some seconds) the additional heat and transfer it further to the common heatsink and ambience. Depending on the system design, removing the common heatsink and TIM is also possible for improved system Zthja, wherein the heat spreader is the primary heatsink and is directly cooled by the fan airflow.

Single-device heat-spreader mounting.
Figure 7: Single-device heat-spreader mounting6

Thermal performance

Figure 8 shows Zthja time-dependent plots for selected through-hole device (THD), BSC SMD, and TSC SMD packages considering an FR4-based PCB design with forced air cooling. The same device inside all shown packages is assumed just as the same power losses. Comparing DDPAK (TSC package) with TO263 (BSC package) on an FR4-based PCB, DDPAK achieves 60% lower Zthja, although the effective cooling area of both packages is quite similar. DDPAK bypasses the bottleneck “thermal vias,” as described in the section before. The graph also illustrates that top-side packages can achieve Zthja values comparable to THDs.

transient thermal impedance junction ambient (Zthja) for multiple packages at forced convection.
Figure 8: Typical transient thermal impedance junction ambient (Zthja) for multiple packages at forced convection

The legend shows that using thin layers of isolation materials with a comparable high λ is the key to achieving good Zthja results. Beyond that, using gap filler and isolation foil with further higher λ will lead to a situation whereby the shown TSC packages deliver lower Zthja than the THD.

Low inductance parasitic advantage in high-frequency operation

Figure 9 demonstrates the effect of package source inductance (LSc) on the turn-on transient. LSc is increased from 0 to 4 nH. The rise of drain current (di/dt) causes an inductive voltage drop over LSc, which subtracts from gate drive voltage and thus reduces the gate current. So the voltage transient takes longer, and the losses increase. The same mechanism but in an opposite manner applies to the turn-off transient.

Example of package source inductance effect.
Figure 9: Example of package source inductance effect on switching on: waveform details (left) and losses (right)

The negative effect of LSc discussed above can be eliminated by using a separate source sense pin (Kelvin source) for controlling the gate (Figure 10, right), which effectively reduces switching losses. By using the source sense connection to drive the gate, the LSc comes outside the gate drive loop. Therefore, its induced voltage peaks will not feed back into the driving circuit as would happen in the standard configuration (Figure 10, left) with only a single source connection to the MOSFET.

Gate drive loop comparison of a standard three-terminal package (left) and a four-terminal package with Kelvin source (right).
Figure 10: Gate drive loop comparison of a standard three-terminal package (left) and a four-terminal package with Kelvin source (right)

It’s important to mention that Kelvin source packages solve the LSc negative effect on the gate drive and switching speed. However, the LSc will still add to the total loop inductance, which is a crucial parameter that causes ringing in fast-switching applications such as server SMPS with wide-bandgap (WBG) switches. For that reason, the package LSc is preferably the lowest even when using a Kelvin source. More details are available in the referenced application note.7


This article discussed the significance of power semiconductor packages in meeting the power and density requirements of server power supplies, specifically for silicon and WBG switches.

A quick introduction to server SMPS applications and trends was presented, followed by a discussion on SMD packages regarding assembly implementations, thermal performance, and low-inductance parasitic advantages in a high-frequency operation.

Table 1 summarizes Infineon’s SMD package portfolio used in server SMPS, comparing their main parameters.

Overview of SMD BSC and TSC packages for server applications.
Table 1: Overview of SMD BSC and TSC packages for server applications. For assessment of package inductance, a device with a similar RDS(on) inside the package is assumed.

To learn more about Infineon’s design solutions for SMPS that meet the increasingly high demands of servers and data centers, please click here. Also, discover our full spectrum of innovative power technologies (Si, SiC, and GaN). For high-voltage power MOSFETs, click here. For WBG solutions, click here.

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1S. Preimel. (2018). “600 V CoolMOS™ G7 and 650 V CoolSiC™ G6 come in a new top-side cooling package – the DDPAK.” Application Note, AN_1802_PL52_1803.

2Infineon Technologies. (2020). “Recommendations for board assembly of Infineon packages with dual row gullwing leads.” Rev. 5.0.

3Infineon Technologies. (2021). “TO-leaded top-side cooled (TOLT) package automotive power MOSFET.” Application Note v1.1, Z8F80044621.

4Infineon Technologies. (2022). “TOLL vs. TOLT.” Application Note, Z8F80127016.

5Infineon Technologies. (2021). “Innovative top-side cooled package solution for high-voltage applications.” Application Note v1.0, AN_2101_PL52_2103_112902.

6S. Preimel. “600 V CoolMOS CFD7 comes in a new top-side cooling package – the QDPAK.” Infineon Technologies. Application Note, to be published soon.7B. Zojer. (2020). “CoolMOS™ gate drive and switching dynamics.” Application Note v1.0, AN_1909_PL52_1911_173913.

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