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The sixth iteration of the peripheral connection specification (PCIe) was released only at the beginning of the year, but the organization responsible for its management is already looking forward to PCIe 7.0.
During the PCI-SIG 2022 developer conference, the PCI Special Interest Group (SIG) announced that it has committed to launching PCIe 7.0 in 2025. The PCI-SIG technical working groups are starting work now, said Al Yanes, president and PCI-SIG chair, to double data speeds to 128 GT / s and up to 512 GB / s bidirectionally via the x16 configuration.
The seventh iteration of PCIe’s PCI-SIG aims to continue to deliver low latency and high reliability targets, improve energy efficiency, and continue to maintain backward compatibility with all previous generations. The next generation of the specification will use 4-level pulse amplitude modulation (PAM4) signaling and will focus on channel and range parameters.
Janes said that PCI-SIG’s confidence in its ability to achieve these goals is based on success with PCIe 6.0. It has moved from NRZ to PAM4 signaling and flow control coding-based coding, which supports PAM4 modulation and works in conjunction with the newly added forward error correction and cyclic redundancy check to allow bandwidth doubling.
“It was a revolutionary transition for us to move from NRZ Z to PAM4,” he said. These features were added without sacrificing latency or backward compatibility.
The goals set for PCIe 7.0 reflect the requirements of emerging PCI-SIG applications, such as 800 G Ethernet, AI and machine learning, cloud computing and even quantum computing, as well as data-intensive applications such as e.g. hyper-scale data centers, high-performance computing, and military and space applications.
“Obviously not everyone needs a PCIe 7.0 or PCIe 6.0 bandwidth,” Janes said. “People who do HPC, artificial intelligence and machine learning are the ones who will adopt higher speeds to achieve bandwidth goals.”
If that wasn’t enough, PCI-SIG would explore the automotive capabilities that were already on the horizon with PCIe 6.0. But the path for implementing PCIe 7.0 in vehicles is not entirely clear, Janes noted. “We focus hard, trying to get there.”
A working group has been set up to focus on the automotive aspect, with the number of sensors generating data in the vehicle being a major factor. Most cars reaching level 2.5 of autonomy have about 30 to 50 sensors that support vehicle functions and speed requirements.
Currently, even PCI 6.0 is not accepted in automotive applications due to the lack of a certificate of reliability required by automakers, such as Automotive Safety Integrity Level (ASIL) D, certified according to ISO 26262. This is one of the strictest levels of integrity of safety for car safety. It takes about a year to get it, Janes explained.
Micron Technology has just announced that its LPDDR5 DRAM memory is now ASIL D certified in anticipation of Level 5 autonomy, which is further down the road than originally expected.
The PCIe bus standard has become central to many other technologies and specifications that facilitate data movement. Both the relatively mature En-Volatile Memory Express protocol and the new but fast-growing Compute Express Link use the ubiquity of PCIe.
– Gary Hilson is the editor-in-chief, focusing on memory and flash technology for the EE Times.
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