Physical analysis of the termination area in case of switching loss

In an article entitled “Influence of the termination area on the switching loss for SiC MOSFET”, the researchers analyzed the impact of the termination area on the parasitic capacities. Simply put, parasitic capacitance is an unavoidable but undesirable capacitance that exists between parts of an electronic component or circuit due to their proximity to each other.

The input capacity, output capacity and reverse transfer capacity depend on the capacity between the three SiC MOSFET pins. Because there is a physical overlap between the shutter bar and the source electrodes, the oxide layer under the door is relatively thicker than the oxide layer of the shutter. Without overlap between the gate and drain electrodes, as well as the gate and source terminals, they contribute very little to the overall capacity. Therefore, the output-to-output capacitance consists of the equivalent capacitance from the active and terminal area.

The team used TCAD Sentaurus to demonstrate the principles of operation of parasitic capacities during SiC MOSFET on and off events. TCAD Sentaurus is an advanced multidimensional simulator that is able to simulate electrical, thermal and optical characteristics of silicon-based devices and is used to develop and optimize semiconductor technologies. Voltage overlap (V_ds) through the device and current_ds) passing through the device leads to switching losses. To illustrate the switching process inside the SiC MOSFET, the channel current (I_ch) is entered through the gate channel.

During the Miller interval of the switching process, the capacity from the inlet to the drain (C_gd) and core area capacity (C_acti) are diluted due to the resistive flow of the discharge current (I_term) of the capacity introduced in the end area (C_term) through the gate channel located in the active area. The scattering current flowing through the gate channel or the channel current (I_ch) in this interval is a combination of current flowing in the end region (I_term) together with the discharge current of the core capacity_acti) and current from east to source_ds).

While for the Miller interval of the shutdown process, instead of flowing through the shutter channel, part of the current flows from the source to the source (I_ds) starts charging the capacity introduced in the active and end area (C_acti and C_term), as shown in the figure below. Here the scattering channel current (I_ch) switches off the currents of C_term and C_acti (i.e., I_ch = I_ds – I_acti – I_term).

During the physical analysis of the end area, the channel current (I_ch) flowing through the input channel of the SiC MOSFET is the main current demonstrating loss of switching, but not measurable current from drain to source (I_ds). Therefore, the expressions for loss of inclusion and exclusion, given the area of ​​termination, are given as:

After combining the above equations for off and on loss expressions, the following equations are defined:

Equations 3 and 4 represent the contribution of switching losses from measurable I_ds during Miller’s on and off processes. Equations 5 and 6 show the charge and discharge of C_acti and C_term. For a given device, the energy stored in the parasitic capacities of the core and the terminal area is fixed with the same blocking voltage, but regardless of I_ds.

As shown in Figure 4, a dual pulse test with separation of the SiC MOSFET in the active region and the end region was constructed to verify the composition of the switching loss. The rated currents of the SiC MOSFET are 1, 3 and 6 A, which is determined when V_ds = 3 V and V_gs = 20 V. Using TCAD Sentaurus simulation, the calculated breakdowns of losses when switching 1-, 3- and 6-A SiC MOSFET below 800, 1000 and 1200 V are shown in the figure below.

The switching loss is broken down to E_ON (And_ds), E_actiE_termand E_OFF (And_ch). The values ​​of E_ON (And_ds), E_actiand E_term are comparative, while E_OFF (And_ch) becomes very low at different blocking voltages and rated currents. As the area for the active region increases for higher current estimates, E_acti increases the share of total switching loss. If a relatively weaker gate driver is used, E_ON (And_ds) and E_OFF (And_ch) will be larger. On the other hand, E_acti and E_term are fixed to a specific MOSFET. For E_OFF of the SiC MOSFET, a small current flows through the shutter channel, generating a small joule heat, but almost all the current charges the C_acti and C_term such as bias current. This leads to a lower value of E_OFF (And_ch). It can be expressed as follows:

Where I am_{g (OFF)} is the discharge current of the gate loop during the shutdown process, it indicates that the shutdown duration is much faster than C_acti and C_term .

Physical insights in the termination area of ​​the SiC MOSFET are simulated using the TCAD Sentaurus and the switching loss model, taking into account the impact of termination regions. It was confirmed that the influence of the termination region on the switching loss cannot be ignored, especially for SiC MOSFET with low current. One of the significant parts of the power-on loss is E_term and E_actiwhich is an inherent loss with or even higher than the commonly used estimate of electrical measurement.

E_ON must include E_term and E_actiwhile E_OFF must turn off E_term and E_acti compared to the conventional estimate of switching losses. Considering C_term further exacerbates the underestimation and overestimation of E_ON and E_OFF, respectively. Inaccurate loss estimation can affect the choice of SiC MOSFET and applied circuit design for specific applications.

¹AQ Huang. “Merits of the new unipolar switching power supply.” IEEE Electron. Device Lett., Vol. 25, no. 5, pp. 298–301, May 2004.