Although silicon is the most widely used semiconductor in electronics, recent studies show that it has some limitations, especially in high-power applications. Bandwidth is an important factor for semiconductor-based circuits, as high bandwidth offers advantages in terms of operation at high temperatures, voltages and frequencies. While silicon has a bandwidth of 1.12 eV, silicon carbide has 3 times the bandwidth value of 3.2 eV, resulting in better performance and efficiency with higher switching frequencies as well as a lower overall footprint.

SiC MOSFETs come with remarkable properties and a single-pole conductor, which reduces their size and improves switching performance. In addition, the size of the SIC MOSFET may be smaller than that of the Si, as theorized in Huang’s merit indicators1 at the same current and voltage values. Due to the smaller size, the total parasitic capacitance is smaller, which allows the SiC MOSFET to achieve a high switching speed and low resistance when switched on. Therefore, SiC-based converters have great potential for use in hybrid / electric vehicles, solar inverters and uninterruptible power supplies.

Previous research has shown that a significant reduction in the size of the SiC chip is considered only for the active region. The completion area, which covers the active area and helps to successfully achieve an almost perfect avalanche breakthrough, cannot be scaled due to the peripheral electric field placed on the boundary of the active area. A team of researchers worked to analyze the parasitic capacitance introduced by the termination region and how it affects the switching loss for SiC MOSFETs.2 This study was supported in part by the National Science Foundation of China and in part by the State Key Laboratory for Broadband Semiconductor Power Electronic Devices. [Original article]

Analysis of SiC MOSFETs in the field of termination

In an article entitled “Influence of the termination area on the switching loss for SiC MOSFET”, the researchers analyzed the impact of the termination area on the parasitic capacities. Simply put, parasitic capacitance is an unavoidable but undesirable capacitance that exists between parts of an electronic component or circuit due to their proximity to each other.

Figure 1: Cross-sectional view of a half-cell step and an end area

The input capacity, output capacity and reverse transfer capacity depend on the capacity between the three SiC MOSFET pins. Because there is a physical overlap between the shutter bar and the source electrodes, the oxide layer under the door is relatively thicker than the oxide layer of the shutter. Without overlap between the gate and drain electrodes, as well as the gate and source terminals, they contribute very little to the overall capacity. Therefore, the output-to-output capacitance consists of the equivalent capacitance from the active and terminal area.

The team used TCAD Sentaurus to demonstrate the principles of operation of parasitic capacities during SiC MOSFET on and off events. TCAD Sentaurus is an advanced multidimensional simulator that is able to simulate electrical, thermal and optical characteristics of silicon-based devices and is used to develop and optimize semiconductor technologies. Voltage overlap (Vds) through the device and currentds) passing through the device leads to switching losses. To illustrate the switching process inside the SiC MOSFET, the channel current (Ich) is entered through the gate channel.

Figure 2: Diagram of the parasitic capacitance circuit, taking into account the end region

During the Miller interval of the switching process, the capacity from the inlet to the drain (Cgd) and core area capacity (Cacti) are diluted due to the resistive flow of the discharge current (Iterm) of the capacity introduced in the end area (Cterm) through the gate channel located in the active area. The scattering current flowing through the gate channel or the channel current (Ich) in this interval is a combination of current flowing in the end region (Iterm) together with the discharge current of the core capacityacti) and current from east to sourceds).

While for the Miller interval of the shutdown process, instead of flowing through the shutter channel, part of the current flows from the source to the source (Ids) starts charging the capacity introduced in the active and end area (Cacti and Cterm), as shown in the figure below. Here the scattering channel current (Ich) switches off the currents of Cterm and Cacti (i.e., Ich = IdsIactiIterm).

Figure 3: Schematic and equivalent scheme of the end region of the SiC MOSFET during the Miller plateau selection of the on (off) and off (below) process

Switching loss modeling for SiC MOSFETs

During the physical analysis of the end area, the channel current (Ich) flowing through the input channel of the SiC MOSFET is the main current demonstrating loss of switching, but not measurable current from drain to source (Ids). Therefore, the expressions for loss of inclusion and exclusion, given the area of ​​termination, are given as:

After combining the above equations for off and on loss expressions, the following equations are defined:

Equations 3 and 4 represent the contribution of switching losses from measurable Ids during Miller’s on and off processes. Equations 5 and 6 show the charge and discharge of Cacti and Cterm. For a given device, the energy stored in the parasitic capacities of the core and the terminal area is fixed with the same blocking voltage, but regardless of Ids.


Figure 4: Separation switching scheme in SiC MOSFET

As shown in Figure 4, a dual pulse test with separation of the SiC MOSFET in the active region and the end region was constructed to verify the composition of the switching loss. The rated currents of the SiC MOSFET are 1, 3 and 6 A, which is determined when Vds = 3 V and Vgs = 20 V. Using TCAD Sentaurus simulation, the calculated breakdowns of losses when switching 1-, 3- and 6-A SiC MOSFET below 800, 1000 and 1200 V are shown in the figure below.

Figure 5: Breakdown of switching losses for different MOSFETs

The switching loss is broken down to EON (Andds), EactiEtermand EOFF (Andch). The values ​​of EON (Andds), Eactiand Eterm are comparative, while EOFF (Andch) becomes very low at different blocking voltages and rated currents. As the area for the active region increases for higher current estimates, Eacti increases the share of total switching loss. If a relatively weaker gate driver is used, EON (Andds) and EOFF (Andch) will be larger. On the other hand, Eacti and Eterm are fixed to a specific MOSFET. For EOFF of the SiC MOSFET, a small current flows through the shutter channel, generating a small joule heat, but almost all the current charges the Cacti and Cterm such as bias current. This leads to a lower value of EOFF (Andch). It can be expressed as follows:

Where I amg (OFF) is the discharge current of the gate loop during the shutdown process, it indicates that the shutdown duration is much faster than Cacti and Cterm .


Physical insights in the termination area of ​​the SiC MOSFET are simulated using the TCAD Sentaurus and the switching loss model, taking into account the impact of termination regions. It was confirmed that the influence of the termination region on the switching loss cannot be ignored, especially for SiC MOSFET with low current. One of the significant parts of the power-on loss is Eterm and Eactiwhich is an inherent loss with or even higher than the commonly used estimate of electrical measurement.

EON must include Eterm and Eactiwhile EOFF must turn off Eterm and Eacti compared to the conventional estimate of switching losses. Considering Cterm further exacerbates the underestimation and overestimation of EON and EOFF, respectively. Inaccurate loss estimation can affect the choice of SiC MOSFET and applied circuit design for specific applications.


1AQ Huang. “Merits of the new unipolar switching power supply.” IEEE Electron. Device Lett., Vol. 25, no. 5, pp. 298–301, May 2004.

2Li et al. “Influence of termination area on switching loss for SiC MOSFET”IEEE Transactions on Electron Devices, Vol. 66, № 2, pp. 1026–1031, February 2019, doi: 10.1109 / TED.2018.2888995.

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