There remains little doubt that silicon carbide, a so-called third-generation, wide-bandgap semiconductor is fulfilling its long-known potential, with the automotive industry having been the very public proving ground for the material in the last five years. SiC-based drivetrain inverters — power converters that convert DC electricity from the battery side into AC required from the motor side — are smaller, lighter, and more efficient than their Si IGBT–based ancestors. 

However, the electrification agenda will not begin and end with cars. Wider transport applications will soon come into view, including trucks and buses, marine and shipping, the further electrification of trains, and even airplanes. On the supply side, grid-connected solar power systems and the transport of energy via high-voltage DC (HVDC) links will also be critical to the generation and distribution of low-carbon energy. 

A common theme across these applications is the potential role for higher system voltages and, hence, higher-voltage power devices. In EVs, the benefit of the shift from 400 to 800 V is predominantly the faster charging rate possible. In solar inverters, an ongoing shift from 1,000-V to 1,500-V systems is reducing the number of PV strings, inverters, cables, and DC junction boxes, all of which result in efficiency and cost savings. In gigawatt HVDC installations, in which the nominal voltage is several hundred kilovolts, a higher individual device rating reduces the number of devices required in a multilevel stack, reducing maintenance and overall system size. 

SiC power devices have the potential to be a key enabler in each of these areas. However, today, the range of SiC devices available on the market is incredibly narrow, from just 650 V to 1,200 V, with just a smattering of 1,700-V devices available, and while 3,300 V looks well within reach technologically, only GeneSiC supplies devices at this voltage level. 

This singular focus on the automotive prizes on offer is, of course, understandable. The race to capture market share of this industry has led to companies fighting to drive up capacity, adopt 200-mm wafers, and drive up yields. This leaves scant room for the substantial R&D activities necessary to open up the high-voltage markets, which are relatively small in comparison. 

Figure 1: The current Si and SiC device landscape, alongside a projection to SiC’s future potential market 

Thankfully, the research sector has been hard at work, and numerous demonstrators of SiC technology at higher voltage have been designed, fabricated, and trialed, giving us a good understanding of the impact that a SiC superjunction (SJ) MOSFET, IGBT, and thyristor might have on these high-voltage applications. 

Up in voltage, not down? 

It is a fairly safe prediction that 650 V will remain a floor for the SiC MOSFET. Figure 2 shows the unipolar limit graph, which maps today’s commercial SiC devices, with their resistance plotted against their blocking voltage. This reveals the limitations of the technology. As the voltage-blocking drift region is reduced to a thickness of just 5 µm at 650 V, the resistance of the device has reduced to such a degree that fixed resistances from the SiC channel region and the substrate dominate, preventing any further downscaling of the resistance. While there appears to be considerable margin for improving 650-V MOSFETs in coming generations, it will be hard to lower these fixed resistances sufficiently far to make the case for a commercial 300-V SiC MOSFET. 

At these low voltages, devices without a channel, such as Qorvo/UnitedSiC’s cascode JFETs, have an RDS(on) advantage: some wafer thinning, allowing for a very low-resistance SiC FET. In reality, given the practical limitations as to how much further the SiC channel mobility can be improved using an industry-compatible method, the SiC JFET may be the only device that could achieve a voltage rating below 600 V.

Current 650- and 1,200-V SiC device landscape.
Figure 2: Current 650- and 1,200-V SiC device landscape, as plotted on a unipolar limit graph 

Scaling up the unipolar SiC MOSFET 

What is implied in Figure 2, by the dash-dot line representing the current SiC technology limit, is that while SiC is a good technology at 650 V and 1,200 V, it has the potential to get even better at higher voltages. As the drift region is scaled to 30 µm to support devices rated 3.3 kV, its resistance eclipses that of the substrate and channel, pushing the devices ever closer to the technology limit. Therefore, in the future, high-voltage SiC MOSFETs honed to the quality of today’s SiC devices would have an even greater advantage over the incumbent Si technologies at voltages up to 10 kV. 

Technologically, there is little preventing the scaling of SiC MOSFET technology. 3.3-kV devices are quite mature in the academic literature,1 and the technology required to make epitaxial layers of a good quality up to about 10 kV already exists. 

However, the economics of a SiC die change at these higher voltages, as modeled using PGC Consultancy’s SiC die cost model. First, the higher the voltage required, the wider the drift region must be to support it, and hence, the greater the epitaxy costs. The effect of this is shown in Figure 3, in which the epitaxy costs can be seen to overtake the substrate as the greatest processing cost by the 60-µm, 6.5-kV device. 

The projected costs of a SiC MOSFET as they are scaled to 15 kV.
Figure 3: The projected costs of a SiC MOSFET as they are scaled to 15 kV. (Post-sorting/-qualification die yield not included. Epi yield modelled on 100-A die and 0.2 defects/cm2.) 

While innovation in multi-wafer epitaxy tools could potentially shrink this cost, a second cost issue caused by a thick drift region’s resistance is inescapable. Each step up in voltage class requires a drift region that is both thicker and lower in doping than the class before. As the voltage is doubled, the resistance will increase by approximately 5.5×.2 To counteract this, and to maintain a given current/resistance rating (100-A die in Figure 3), the die size must be increased proportionally. However, enlarging the die has a compounded effect on yield and, hence, on costs. A smaller number of die is produced per wafer, while the proportion written off by defects from the epi are much higher — even if low defect densities could be maintained (0.2 defects/cm2 in Figure 3). 

The result of these effects is seen in Figure 3, captured in the rising epitaxy yield cost at higher voltage, and the skyrocketing die cost, which, by 15 kV, reaches 75× that of the 650-V die. 

Zooming back out, SiC MOSFETs look to be a viable proposition up to 6.5 kV, maybe even to 10 kV, but the costs associated with these devices may prevent higher-voltage implementation. 

Bipolar devices are the solution

History repeats itself, of course, and the key to reducing the drift region resistance, and hence the die size, is to adopt bipolar solutions, IGBTs, and thyristors, as seen in Figure 4. The compromise of the bipolar device is to accept slower switching capability and higher switching losses compared with unipolar MOSFETs in exchange for the conductivity-modulated, low-resistance drift regions. This tradeoff is not likely to be an issue for any applications that would need 10-kV–plus SiC devices; HVDC converters operating at 50/60 Hz have little need for fast, low-loss switching. Indeed, they already use Si IGBTs and thyristors. 

Cross-sections of the power devices.
Figure 4: Cross-sections of the power devices discussed in this article 

However, these devices require a number of technological leaps from today’s SiC MOSFETs. The first issue is that conventional N-channel IGBTs and P-base thyristors both require a highly P-type doped (P+) collector region. P+ substrates are not available due to the challenge of incorporating the P dopant, aluminium, into the substrate during the seeded sublimation process.3 As mentioned above, with little motivation from SiC material suppliers to solve this problem right now, other solutions have had to be found. This has typically involved growing all the device layers on an N+ substrate and then grinding off the original wafer — using the same process used to thin a MOSFET’s substrate. Using this technique, a number of IGBTs have been demonstrated — at 6.5 kV,4 15 kV,5 and 27.5 kV6 — and thyristors at 7.6 kV7 and 20 kV.8 

A second issue is the carrier lifetime of the SiC, a value that must be maximized to encourage conductivity modulation. In the world of Si fabrication, the usual problem is that the material is so pure that defects need to be introduced to reduce the lifetime, thus reducing the switching losses. In SiC, the opposite is true. Defects, known as carbon vacancies, are introduced in the epitaxy process, resulting in a very low lifetime (1–2 µs). As such, prior to IGBT/thyristor fabrication, a lifetime enhancement process — a long oxidation process — is the most widely used to drive carbon into the drift region to fill the vacancies and increase the lifetime to 10–20 µs. 

Assuming both these processes can be mastered and carried out at scale, then good-quality bipolar devices are possible in SiC, which could reduce die area at a given voltage by as much as 10×. Unmentioned until now, PIN diodes could be the first and easiest high-voltage SiC devices to be brought to market, as these can be produced directly on N+ substrates. 

Something in between? 

SJ devices are another potential way to reduce the resistance of a SiC MOSFET, a middle ground between the fully unipolar MOSFET and the IGBT. Yet the familiar deep-implant process, used to make the narrow N-type and P-type columns in Si,9,10 is not possible in SiC, its high atom density resulting in very shallow implants. Therefore, alternative fabrication methods have been devised to create the vertical p-n pillars required, including etching trenches into the SiC and refilling them with epitaxy. Another method2 looks to implant into the trench sidewalls. These methods are still in their infancy, with technological challenges still to overcome, but they demonstrate that SiC SJ devices are possible. 

Conclusion 

SiC’s great advantage over other wide-bandgap materials is that its substrates are freestanding and it has a native SiO2 oxide. This makes it possible to replicate the full array of well-known Si power device topologies, all shifted up in voltage. The electric vehicle boom was the catalyst needed to kickstart the SiC industry, encourage competition in the market, and demand higher-quality material at a lower price and at a larger scale. Yet it is also the reason that the expansion of the SiC voltage range is a secondary priority behind winning market share at 650 and 1,200 V. However, in the fullness of time, SiC will impact the grid, renewables, and transport sectors. Indeed, many of the solutions as to how to produce the next generation of SiC devices are already clear; it is just a matter of time until they can be commercially realized. 

References 

1Kimoto, T., & Yonezawa, Y. (2018). “Current status and perspectives of ultrahigh-voltage SiC power devices.” Materials Science in Semiconductor Processing, Vol. 78, pp. 43–56. 

2Baker et al. (2021). “Optimization of 1700-V 4H-SiC Superjunction Schottky Rectifiers With Implanted P-Pillars for Practical Realization.” IEEE Transactions on Electron Devices, Vol. 68, No. 7, pp. 3497–3504. 

3Kimoto, T., & Cooper, J.A. (2014). Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications. IEEE. 

4Watanabe et al. (2016). “6.5 kV n-Channel 4H-SiC IGBT with Low Switching Loss Achieved by Extremely Thin Drift Layer.” Materials Science Forum, Vol. 858, pp 939–944. 

5Ryu et al. (2012). “Development of 15 kV 4H-SiC IGBTs.” Materials Science Forum, Vol. 717, pp. 1135–1138. 

6Brunt et al. (2014). “22 kV, 1 cm2, 4H-SiC n-IGBTs with improved conductivity modulation.” 2014 IEEE 26th International Symposium on Power Semiconductor Devices & ICs (ISPSD), pp. 358–361. 

7Xu et al. (2018). “High-Voltage 4H-SiC GTO Thyristor with Multiple Floating Zone Junction Termination Extension.” 2018 1st Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), pp. 149–152. 

8Cheng et al. (2013). “20 kV, 2 cm2, 4H-SiC gate turn-off thyristors for advanced pulsed power applications.” 2013 19th IEEE Pulsed Power Conference (PPC), pp. 1–4. 

9Deboy et al. (1998). “A new generation of high voltage MOSFETs breaks the limit line of silicon.” International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), pp. 683–685. 

10Lorenz et al. (1999). “CoolMOS – a new milestone in high voltage power MOSFETs.” Proc. 11th International Symposium Power Semiconductor Devices and ICs (ISPSD), pp. 3–10. 

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