Thanks to a better figure of merit,1 Broadband semiconductors such as gallium nitride offer a higher power density than silicon, taking up less matrix area and therefore requiring a smaller package. Assuming that the area occupied by the device is the main factor determining the thermal characteristics, it is reasonable to assume that the device with less power leads to higher thermal resistance.3.4 This article will demonstrate how GaN FETs for chip packaging (CSP) offer thermal performance at least equal to, if not better than, silicon MOSFETs. Thanks to their superior electrical performance, the size of the GaN FET can be reduced by increasing the power density while respecting temperature limits. This behavior will be demonstrated through detailed 3D simulations of the finite elements of the PCB layout, while providing experimental verification to support the analysis. Read the original article here.2

Thermal control of power devices

The electronics market requires smaller, more efficient and more reliable devices. Key factors in meeting these stringent requirements are high power density (capable of reducing both footprint and solution costs) and excellent heat management (capable of keeping device temperatures under control). The three main requirements of the heat management system for power semiconductors are the following:

  1. Heat must be dissipated from the device to the environment with a thermal resistance low enough to prevent the transition temperature (TJ.) from an increase beyond a certain limit. Due to the deterioration factor, TJ. it is usually lower than the value of the datasheet.
  1. Electrical insulation must be provided between the supply circuit and the environment.
  1. The thermally induced mechanical stress due to the mismatch of the coefficient of thermal expansion of the material must be absorbed.

The most common heat management system for power supplies is shown in Figure 1. It consists of a radiator (which transfers heat from the power semiconductor to the environment) and an electrical insulator (thermal interface material or TIM) to separate the metal radiator from the semiconductor node. Because most dielectric materials have low thermal conductivity, there is a trade-off between electrical insulation and thermal resistance.

Figure 1: The most common heat management system for CSP GaN FETS

In real systems, power supplies are often available in a package consisting of multiple metal and dielectric layers and are mounted on printed circuit boards, which also contain multiple layers of metal and dielectrics. The radiator is attached to this module, which makes it quite complicated. Although the widespread use of SMD components and the reduction in package size have made heat management increasingly complex, thanks to broadband semiconductors, it is now possible to easily achieve a power density of 2 kW / in.3 in cost-effective power converter solutions.5

The introduction of GaN FETs offered in CSP packages, including a passivated matrix with solder or rod irregularities, further complicated thermal management, but also brought immediate improvements in performance, reliability and cost. Figure 2 shows a half-bridge based on EPC2059 CSP GaN FET with a matrix size of 2.8 × 1.4 mm. The right side of the image shows the underside of the printed circuit board with the solder strips.

Figure 2: EPC2059 CSP GaN FET on a standard PCB

Although reduced losses of GaN FETs are sufficient to ensure proper heat management in some applications, radiator-based solutions (as shown in Figure 1) are needed for high power converters.

Thermal analysis

Cross-sections of PCBs and FETs with a radiator mounted on them are shown in Figure 3. Heat can follow multiple paths: It can flow from the top of the die, from the four sides of the die, and through a copper circuit board that distributes heat. to TIM and to the radiator. Although TIM usually has a relatively low thermal conductivity compared to a semiconductor matrix, the latter thermal path is still significant.

Multiple heat flow paths from the device to the radiator.
Figure 3: Multiple heat flow paths from the device to the radiator

A simplified model of the system used for FEM analysis is shown in Figure 4, while Figure 5 shows the FET model based on EPC2059.

Simulation model.
Figure 4: View of the simulation model
Figure 5: Simulated temperature profile

The simulation is based on three parameters: the distance between the top of the FET to the bottom of the radiator, the thermal conductivity of the TIM and the radius of the applied TIM. The simulation results are shown in Figure 6, with the values ​​of the thermal resistance from the FET junction to the radiator surface as a function of the TIM diameter, and in Figure 7, where Rθ, JS is now a function of the circular cross-sectional area of ​​the TIM cylinder.

Predicted Rθ, JS as a function of TIM diameter.
Figure 6: Predicted Rθ, JS as a function of TIM diameter
TIM zone function.
Figure 7: Predicted Rθ, JS as a function of the TIM zone

The curves in Figure 6 show that the difference between the peak and mean values ​​is higher for the low kTEAM material, stating that most of the heat escapes through the solders at the bottom of the component.

It should be noted that the curves in Figure 7 show a knee with a diameter between 4- and 5 mm, and above 8 mm there is no additional increase in Rθ, JS. Therefore, the main benefit is below the TIM area of ​​about 20 mm2 for kTEAM = 10 W / mK and 30 mm2 for kTEAM = 3.5 W / mK. When the gap between the die and the radiator is reduced, the elbow is shifted to the left and Rθ, JS the values ​​are reduced.

Experimental results

The experimental setup is based on the same PCB used for the thermal model shown in Figure 8. A thermocouple is placed in a small hole drilled in the center of the copper heat distributor, while a second thermocouple is mounted on the opposite side of the sprinkler.

Tested PCB.
Figure 8: Tested PCB

A Kelvin connection was used to measure the high voltage drop. Knowing this and the current supplied, an accurate measurement of the power dissipated in the active region of the FET can be obtained. To measure the transition temperature of the GaN FET, a Type K thermocouple with 36-AWG insulated conductors was placed in contact with the bottom of the FET using a low melting point solder.

The table in Figure 9 compares the measured results with the peak and mean values ​​obtained from the simulation models. For kTEAM = 3.5 W / mK, the measured results and the simulated values ​​are quite similar. However, for kTEAM = 10 W / mK, the error is significantly higher. Further analysis showed that this error was partly due to the failure to read the solder mask layer in the simulation, as this would have an increasing effect as kTEAM increases.

measured and simulated values ​​of thermal resistance.
Figure 9: Comparison between measured and simulated values ​​of thermal resistance


1L.idow et al. (2020). GaN transistors for efficient power conversion, third edition. Wiley.

2Glaser et al. (2021). “Simply high-performance thermal control of GaN FETs on a chip scale.” 2021 IEEE Conference and Exhibition on Applied Power Electronics (APEC).

3de Rooij et al. (2018). “High-performance thermal solution for high-power eGaN FET high-power converters.” International Exhibition and Conference on Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM Europe), pp. 944-950.

4Sawle et al. (2001). “DirectFETTM – a patented new source, mounted power supply package for board-mounted power supply.” Power conversion and intelligent motion (PCIM).

5Monolithic energy systems. (2020). MPC1100A-54-0000 Datasheet, Rev. 1.1.

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